Command-Line Interface

XiBIF – Xilinx Board Interface

usage: xibif [-h] [-v] [-p PROJECT]
             [--verbosity {debug,info,warning,error,none}] [--summary]
             {new,build,flash,register,simulation,testbench,log,report,start,upgrade,settings}
             ...

Named Arguments

-v, --version

show program’s version number and exit

-p, --project

Specify the XiBIF project file to use

--verbosity

Possible choices: debug, info, warning, error, none

Set the verbosity of the console output

Default: info

--summary

Show only a summary of the log output

Default: False

subcommands

command: Possible choices: new, build, flash, register, simulation, testbench, log, report, start, upgrade, settings

Sub-commands

new

Create a new XiBIF project

xibif new [-h] -n NAME [-p PATH] [--force | --nuke] -b
          {zyboz710,zyboz720,zedboard,zcu102,zcu104,kv260} [-x XILINX]
          [-v {2023.1,2023.2,2024.1,2024.2,2025.1,2025.2}] [--dev-mode]

Named Arguments

-n, --name

Name of the project. This name will be used for the tooling project files

-p, --path

The path to the directory in which to create the project

--force

Overwrite an existing XiBIF project (less destructive than –nuke)

Default: False

--nuke

Completely remove an existing XiBIF project (more destructive than –force)

Default: False

-b, --board

Possible choices: zyboz710, zyboz720, zedboard, zcu102, zcu104, kv260

Name of the FPGA board for this project

-x, --xilinx

Path to the Xilinx installation folder

Default: /opt/Xilinx

-v, --version

Possible choices: 2023.1, 2023.2, 2024.1, 2024.2, 2025.1, 2025.2

Xilinx tooling version to use

--dev-mode

Create a project in development mode (linking to the source files instead of copying them)

Default: False

build

Run all build steps for the XiBIF project

xibif build [-h] [--nowarn] [--noreport-vivado] [--fix-vitis]
            [--stage {vivado:blockdesign,vivado:synthesize,vivado:implement,vivado:bitstream,vivado:export,vivado:reportTiming,vitis:update,vitis:build,vitis:export,vitis:bootfile,vitis:updateLaunch} [{vivado:blockdesign,vivado:synthesize,vivado:implement,vivado:bitstream,vivado:export,vivado:reportTiming,vitis:update,vitis:build,vitis:export,vitis:bootfile,vitis:updateLaunch} ...]]
            [--from {vivado:blockdesign,vivado:synthesize,vivado:implement,vivado:bitstream,vivado:export,vivado:reportTiming,vitis:update,vitis:build,vitis:export,vitis:bootfile,vitis:updateLaunch}]
            [--to {vivado:blockdesign,vivado:synthesize,vivado:implement,vivado:bitstream,vivado:export,vivado:reportTiming,vitis:update,vitis:build,vitis:export,vitis:bootfile,vitis:updateLaunch}]

Named Arguments

--nowarn

Disable the warnings about Vitis bugs and old registers

Default: False

--noreport-vivado

Do not generate output reports for Vivado

Default: False

--fix-vitis

Try to fix Vitis workspace in case it got corrupt

Default: False

--stage

Possible choices: vivado:blockdesign, vivado:synthesize, vivado:implement, vivado:bitstream, vivado:export, vivado:reportTiming, vitis:update, vitis:build, vitis:export, vitis:bootfile, vitis:updateLaunch

Build Vivado/Vitis project with the provided stage(s)

Default: []

--from

Possible choices: vivado:blockdesign, vivado:synthesize, vivado:implement, vivado:bitstream, vivado:export, vivado:reportTiming, vitis:update, vitis:build, vitis:export, vitis:bootfile, vitis:updateLaunch

Build the Vivado/Vitis project starting with the provided stage

--to

Possible choices: vivado:blockdesign, vivado:synthesize, vivado:implement, vivado:bitstream, vivado:export, vivado:reportTiming, vitis:update, vitis:build, vitis:export, vitis:bootfile, vitis:updateLaunch

Build the Vivado/Vitis project stopping with the provided stage

flash

Flash the FPGA with the generated bitstream

xibif flash [-h] [-hw HARDWARE_SERVER] [-p PORT]

Named Arguments

-hw, --hardware-server

Hostname or IP address of the computer running hardware server

Default: 127.0.0.1

-p, --port

Port of the hardware server

Default: 3121

register

Update the XiBIF Registers from the register files

xibif register [-h] [-s] [-u] [-c]
               [--enable-custom ENABLE_CUSTOM | --disable-custom]

Named Arguments

-s, --stream

Generate the XiBIF stream registers

Default: False

-u, --user

Generate the XiBIF user registers

Default: False

-c, --custom

Generate the custom registers

Default: False

--enable-custom

Enable generation of custom registers (provide file name)

--disable-custom

Disable generation of custom registers

Default: False

simulation

Simulate all VHDL testbenches

xibif simulation [-h] [-c | -l | -t TEST] [-g] [-s {modelsim,ghdl,nvc}]

Named Arguments

-c, --compile

Compiles simulation libraries (xilinx and vunit)

Default: False

-l, --list

List all available testbenches and testcases

Default: False

-t, --test

Run only the specified testbench and testcase

-g, --gui

Open the GUI for the simulation (only valid with -t)

Default: False

-s, --simulator

Possible choices: modelsim, ghdl, nvc

Simulator that shall be used (must be available on the path)

Default: modelsim

testbench

Generate a testbench from a VHDL file

xibif testbench [-h] -f FILE [-c CLOCK] [-rn RESET_NEGATIVE]
                [-rp RESET_POSITIVE]

Named Arguments

-f, --file: Name of the VHDL file to generate a testbench for
-c, --clock: Name of clock signal(s)
-rn, --reset-negative: Name of negative reset signal(s)
-rp, --reset-positive: Name of positive reset signal(s)

log

Show the latest log file

xibif log [-h]

report

Report an issue to XiBIF’s GitLab page

xibif report [-h]

start

Start a tool

xibif start [-h] {vivado,vitis,hw_server}

Positional Arguments

tool

Possible choices: vivado, vitis, hw_server

Tool to start

upgrade

Upgrade the VHDL and C source-files to the newest XiBIF version

xibif upgrade [-h]

settings

Change the settings of the XiBIF project

xibif settings [-h] [--mac MAC] [--ip IP] [--netmask NETMASK]
               [--gateway GATEWAY] [--timeout_dhcp TIMEOUT_DHCP]
               [--timeout_connection_drop_ms TIMEOUT_CONNECTION_DROP_MS]
               [--connection_drop_flush_fifo {True,False}]
               [--timeout_axi_firewall_clocks TIMEOUT_AXI_FIREWALL_CLOCKS]
               [--enable_webserver {True,False}]

Named Arguments

--mac

MAC address (type: MacAddress, default: PydanticUndefined)

--ip

Default IP address (type: IPv4Address, default: 192.168.1.10)

--netmask

Default network mask (type: IPv4Address, default: 255.255.255.0)

--gateway

Default gateway (type: IPv4Address, default: 192.168.1.1)

--timeout_dhcp

DHCP timeout in seconds (type: int, default: 10)

--timeout_connection_drop_ms

Connection drop timeout in milliseconds (type: int, default: 1000)

--connection_drop_flush_fifo

Possible choices: True, False

Flag to flush FIFO on connection drop (type: bool, default: False)

--timeout_axi_firewall_clocks

Timeout for AXI Firewall in clock cycles (type: int, default: 100)

--enable_webserver

Possible choices: True, False

Enable embedded web server for register access (type: bool, default: True)